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    • 专利摘要:
    A method for producing a semiconductor device (100), comprising: - producing a stack comprising a first crystalline semiconductor portion (114) intended to form a channel and disposed on at least a second portion that can be selectively etched vis-à-vis the first portion, - realization of a dummy gate and external spacers (112), - etching of the stack, a remaining portion of the stack under the dummy gate and external spacers being retained - Source / drain realization (118, 120) by epitaxy from the remaining part of the stack; - removal of the dummy gate and the second portion, - oxidation of portions of the source / drain from parts of the source / drain revealed by the deletion of the second portion, forming internal spacers (126), - realization of a grid (128) electrically isolated from the source / drain by the external and internal spacers.
    公开号:FR3060841A1
    申请号:FR1662532
    申请日:2016-12-15
    公开日:2018-06-22
    发明作者:Shay REBOH；Emmanuel Augendre；Remi COQUAND
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): BREVALEX Limited liability company.
    (3+ METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS.
    FR 3 060 841 - A1 (3 /) Method for producing a semiconductor device (100), comprising:
    making a stack comprising a first crystalline semiconductor portion (114) intended to form a channel and disposed on at least a second portion which can be selectively etched with respect to the first portion,
    - creation of a dummy grid and external spacers (112),
    - etching of the stack, a remaining part of the stack under the dummy grid and the external spacers being preserved,
    - Realization of source / drain (118, 120) by epitaxy from the remaining part of the stack;
    - removal of the dummy grid and the second portion,
    - oxidation of portions of the source / drain from portions of the source / drain revealed by the removal of the second portion, forming internal spacers (126),
    - Production of a grid (128) electrically isolated from the source / drain by the external and internal spacers.

    i
    METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SPACERS
    SELF-ALIGNED INTERNS
    DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to a method for producing a semiconductor device, such as a GAA-FET transistor (“Gate-AII-Around Field Effect Transistor”, or self-closing field effect transistor), with internal spacers aligned with each other.
    In a GAA-FET type transistor, the gate of the transistor is formed all around the channel such that the channel is surrounded or coated by the gate. The advantage of such a transistor, compared to a conventional MOSFET, is to improve the electrostatic control of the channel by the gate (which makes it possible to reduce the leakage currents), in particular when the transistor is completely deserted (for example of the type FDSOI, or “Fully-Depleted Silicon On Insulator).
    It is known to make a GAA-FET type transistor comprising a stack of several semiconductor nanowires together forming the transistor channel. This configuration makes it possible to obtain a good compromise between the electrostatic control and the desired control current in the transistor.
    The addition of a constraint in the transistor channel contributes to the improvement of the performances of the transistor. This constraint is preferably uniaxial and parallel to the direction of movement of the charge carriers in the channel. A compression stress applied to the channel improves the mobility of the charge carriers in a P-type transistor, while a voltage stress will have a beneficial effect in a N-type transistor.
    Document US 2014/0054724 A1 describes a process for producing a GAA-FET transistor. In such a transistor, the electrical insulation between the gate and the source and drain regions is ensured by external spacers formed on the initial material stack used for producing the active area of the transistor, as well as by internal spacers. made within this stack. These internal spacers are necessary to reduce the capacitive effects between the gate and the source and drain regions. In this document, the internal spacers are produced by etching, in the semiconductor located against the nanowire (s) of the channel, one or more cavities intended to be aligned with respect to the external spacers, then by performing a oxidation of the semiconductor walls of the cavity (ies). This or these cavities are then filled with the grid materials.
    The process described in this document however poses a problem. Indeed, since the cavity or cavities formed within the stack for the production of the internal spacers are obtained by etching without stop layer, the alignment sought between the internal edges of the external spacers and the walls of the cavities is difficult to obtain because it depends on the duration of implementation of the engraving. In practice, the internal spacers obtained are not precisely aligned either with the external spacers, or one above the other. This represents a source of variability in the electrical characteristics of the transistor thus produced, in particular because the variations in the dimensions of the internal spacers directly influence the length of channel obtained.
    STATEMENT OF THE INVENTION
    An object of the present invention is to propose a method for producing a semiconductor device suitable for producing a GAA-FET transistor and the internal spacers of which are produced in a self-aligned manner with respect to each other and compared to external spacers.
    For this, the present invention provides a method for producing a semiconductor device, comprising at least the implementation of the following steps:
    - Production, on a substrate, of a stack comprising at least a first portion of crystalline semiconductor intended to form a channel of the semiconductor device and disposed on at least a second portion of at least one material capable of being etched selectively with respect to the semiconductor of the first portion;
    - Realization, on part of the stack, of a dummy grid and of external spacers between which the dummy grid is arranged;
    - Etching of the stack such that only a remaining part of the stack covered by the dummy grid and by the external spacers is kept;
    - Realization of source and drain regions by semiconductor epitaxy from at least the remaining part of the stack;
    - removal of the dummy grid and the second portion;
    oxidation of portions of the source and drain regions from parts of a face of each of the source and drain regions revealed by the removal of the second portion, the oxidized portions forming internal spacers;
    - Creation of a grid between the external spacers, covering the channel and electrically isolated from the source and drain regions by the external spacers and the internal spacers.
    Thus, the surfaces from which the internal spacers are made correspond to the surfaces of the stack formed by the etching implemented using the dummy grid and the external spacers as an etching mask. Thus, these surfaces are aligned with respect to the external walls of the external spacers, which makes it possible to obtain self-alignment of the internal spacers with one another and with respect to the external spacers. This self-alignment is obtained regardless of the number of first portions of semiconductor used to make the channel.
    With such a production method, the internal spacers may have a surface stopping perpendicular to the internal walls of the external spacers, that is to say the walls of the external spacers in contact with the dummy grid, and the self-realization aligned internal spacers then does not change the channel length of the device and does not impact the electrical performance of the semiconductor device.
    The internal spacers correspond to the elements intended to electrically isolate the grid from the source and drain regions within the stack from which the semiconductor device is made. The internal spacers are disposed at least in part in source and drain extension regions, between the channel and the source and drain regions.
    The external spacers correspond to the elements intended to electrically isolate the grid from the source and drain regions around the stack from which the semiconductor device is made. The external spacers cover at least a portion of the source and drain extension regions.
    In addition, compared to internal spacers which would be produced by deposition, the implementation of an oxidation has the advantage of reducing the implementation constraints for the production of internal spacers, such as for example the dimensions or the ratio of form of internal spacers achievable because the production of internal spacers by deposition would impose constraints on the thickness of material deposited relative to the dimensions of the locations of the internal spacers. In addition, such an embodiment of internal spacers by deposition of a dielectric material would also require the implementation of a step of etching the dielectric material deposited outside the locations provided for the internal spacers. Such a removal step is not necessarily implemented when the internal spacers are produced by oxidation because oxide does not form on all the materials present.
    The semiconductor of the source and drain regions may be able to oxidize more quickly than the semiconductor of the first portion.
    In that case :
    - when the semiconductor device is an N-type transistor, the semiconductor of the first portion, for example silicon, can be intentionally undoped and the production of the source and drain regions comprises N-type doping ( for example, in-situ doping during the epitaxy of the source and drain regions) of the semiconductor (for example silicon) of the source and drain regions, or
    - when the semiconductor device is a P-type transistor, the semiconductor of the first portion can be silicon or SiGe, and the semiconductor of the source and drain regions can be SiGe comprising a higher proportion of germanium to that of the semiconductor of the first portion.
    Thus, when the semiconductor device corresponds to an N-type transistor, the difference in oxidation speed between the semiconductor of the first portion and that of the source and drain regions can be advantageously obtained thanks to a difference of semiconductor doping (the N doped semiconductor oxidizes faster than the intentionally undoped semiconductor).
    When the semiconductor device corresponds to a P-type transistor, the difference in oxidation speed between the semiconductor of the first portion and that of the source and drain regions can advantageously be obtained thanks to the difference in concentrations, or of proportions, of germanium in semiconductors (the one with the highest concentration of germanium oxidizing faster and / or at lower temperature than the other semiconductor).
    When the semiconductor device is an N-type transistor, the dopants of the semiconductor in the source and drain regions can be phosphorus or arsenic atoms.
    When the semiconductor device is a P-type transistor, the material of the second portion can be SiGe, and a proportion of germanium in the semiconductor of the source and drain regions can be at least 5% lower by compared to that in the SiGe of the second portion.
    The oxidation of the portions of the source and drain regions can be carried out at a temperature of between approximately 700 ° C. and 900 ° C. At such temperatures, the diffusion of dopants in the device channel is limited. In addition, the implementation of oxidation at such temperatures is advantageous because the oxidation selectivity obtained thanks to the different dopings and / or to the different compositions of the materials is increased.
    The method can also include the implementation, between the steps of oxidizing the portions of the source and drain regions and making the grid, the implementation of a step of removing an oxidized part of the material of the first portion. When the semiconductor of the source and drain regions is able to oxidize more quickly than the semiconductor of the first portion, this oxidized part of the material of the first portion can therefore be minimized in order to limit the impact of oxidation on the first portion of material.
    The method can also comprise, after the removal of the oxidized part of the material from the first portion, a step of depositing a constrained semiconductor material around the first portion. In this case, the oxidation of the first portion and the removal of the oxidized portion of the first portion serve to achieve a thinning of the first portion. After this thinning, it is possible to deposit around the remaining part of the first portion a constrained semiconductor material, for example SiGe bringing a compressive stress to the channel.
    The method may also include, between the step of etching the stack and the step of producing the source and drain regions, the implementation of the steps of:
    - deletion of the second portion,
    - deposit of at least one material, different from that of the second portion and capable of being selectively etched with respect to the semiconductor of the first portion, in at least one space formed by the removal of the second portion, and the material deposited in the space formed by the removal of the second portion can be removed after the removal of the dummy grid.
    Thus, it is possible to carry out the epitaxy of the source and drain regions in the presence of a material which cannot be obtained in the initial stack, such as for example a dielectric material such as S1O2.
    The realization of the source and drain regions can comprise at least the implementation of a first epitaxy from the remaining part of the stack, forming a first part of the source and drain regions, then a second epitaxy from the first part of the source and drain regions, forming a second part of the source and drain regions. By thus realizing the source and drain regions in the form of two distinct epitaxial parts, it is possible to implement these epitaxies such that the materials of the two epitaxies have different properties.
    The first epitaxy can be implemented such that the first part of the source and drain regions comprises a semiconductor capable of oxidizing faster than that of the second part of the source and drain regions.
    Thus, the first epitaxy can be implemented such that the first part of the source and drain regions comprises semiconductor, for example silicon, including carbon atoms. In this case, this first part of the source and drain regions may have the property of oxidizing at a lower temperature (behavior similar to SiGe). In addition, this first part of the source and drain regions makes it possible to reduce the diffusion of dopants (those present in the source and drain regions) in the channel during the epitaxy of the second part of the source and drain regions. drain.
    It is also possible, when the source and drain regions comprise SiGe, that the first and second epitaxies are implemented such that the proportion of germanium in the semiconductor of the first part of the source and drain regions is greater than that in the semiconductor of the second part of the source and drain regions. In this case, the material of the first part of the source and drain regions has the property of oxidizing faster than that of the second part of the source and drain regions. The oxidation rate of the source and drain regions is therefore reduced after reaching the second part of the source and drain regions. This configuration therefore makes it possible to automatically limit the depth (dimension parallel to the largest dimension, or length, of the nanowires) of the internal spacers within the source and drain regions.
    The second portion can comprise a crystalline material, and the epitaxy forming the source and drain regions can be implemented from at least the crystalline materials of the second portion and of the first portion. Thus, the source and drain epitaxy can be implemented from a surface entirely formed of crystalline materials because the crystalline property of the semiconductor of the first portions is not interrupted by the presence of one or more second portions of non-crystalline material. The source and drain regions are thus formed by a coherent crystalline material, with no crystallinity defect due to the second portion (s).
    When the material of the substrate on which the stack is placed is also a crystalline material, the surface of this material is also used for the growth of the crystalline material of the source and drain regions.
    The epitaxy of the source and drain regions can be implemented such that the semiconductors of the source and drain regions and of the first portion have a difference in mesh parameters inducing a stress in the channel. The addition of such a constraint in the channel contributes to the improvement of the performances of the transistor. This constraint is preferably uni-axial and parallel to the direction of movement of the charge carriers in the channel. When the semiconductor device corresponds to a P-type transistor, this stress can correspond to a compression stress applied to the channel, which makes it possible to improve the mobility of the charge carriers in the transistor. When the semiconductor device corresponds to an N-type transistor, this constraint can correspond to a voltage constraint.
    The addition of a constraint in the channel is preferably carried out when the epitaxy forming the source and drain regions is implemented from at least the crystalline materials of the second portion and of the first portion, that is to say that is to say when the second portion comprises a crystalline material and therefore that the source and drain regions are obtained by growth from a crystalline interface which is not interrupted by the presence of a non-crystalline material. Indeed, a constraint in the channel based on a difference in lattice parameters between the semiconductor of the channel and that of the source and drain regions strongly depends on the crystalline quality of the semiconductor forming the source and drain regions . Source and drain regions comprising a coherent or continuous crystalline semiconductor without defect in crystallinity makes it possible to maximize this constraint.
    The stack produced initially may comprise several first portions of semiconductor each forming a nanowire disposed between two second portions. In the initial stack, two neighboring nanowires are spaced from each other by one of the second portions.
    The semiconductor device is advantageously a transistor
    GAA-FET.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given for purely indicative and in no way limiting, with reference to the appended drawings in which:
    FIGS. 1A to 1H represent the steps of a method for producing a semiconductor device, object of the present invention, according to a first embodiment,
    FIGS. 2A and 2B represent a part of the steps of a method for producing a semiconductor device, object of the present invention, according to a second embodiment,
    - Figures 3A and 3B show a part of the steps of a method for producing a semiconductor device, object of the present invention, according to a third embodiment.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    First of all, reference is made to FIGS. 1A to 1H which represent the steps of a method for producing a semiconductor device 100, corresponding here to a P-type GAA-FET transistor, according to a first embodiment.
    ίο
    As shown in FIG. 1A, the device 100 is produced from a stack 102 of layers of different materials arranged on a substrate 104. In the first embodiment described here, the substrate 104 corresponds to a solid substrate, or " bulk ”, of semiconductor, for example of silicon or of SiGe, on which is disposed the stack 102 comprising layers 106, 108 of two different materials arranged alternately one above the other. Each of the layers 108 is intended to form a semiconductor nanowire of the channel of the device 100 and is arranged between two layers 106 comprising a material capable of being selectively etched relative to that of the layers 108. In the first embodiment described here , the stack 102 comprises three layers 108 as well as four layers 106 arranged in an alternating manner such that each of the layers 108 is disposed between two layers 106.
    As a variant, the substrate used can also correspond to an SOI substrate (silicon on insulator), with in this case the reference 104 which designates the buried dielectric layer, or BOX ("Buried Oxide") of the SOI substrate and the first layer 106 ( that disposed against layer 104) which designates the surface layer, or thin layer, of the SOI substrate.
    The term nanowire is used here to denote any portion of material of nanometric dimensions and of elongated shape, whatever the shape of the section of this portion. Thus, this term designates as many portions of elongated material of circular or substantially circular section, but also portions of material in the form of nano-beams or nano-bars comprising for example a rectangular or substantially rectangular section.
    In the example described here, the substrate 104 and the layers 108 comprise silicon and the layers 106 comprise SiGe with a proportion of germanium for example of between approximately 30% (Sio, 7Geo, 3) and 60% (Sio, 4Geo , 6).
    The stack 102 is engraved in the form of an elongated portion as shown in FIG. IA. The width of this portion, which corresponds to the dimension along the Y axis, is equal to the desired width of the nanowires of the device channel
    100 which will be formed by the portions of the layers 108 obtained at the end of this etching.
    A dummy grid 110 is then produced, for example by lithography and etching, on the stack 102, at the location intended for the future grid of the device 100. The dummy grid 110 is disposed above the parts of the layers 108 intended to forming the nanowires, that is to say the channel of the device 100, and parts of the layers 106 between which these parts of the layers 108 are located, and also covers lateral flanks of these parts of the layers 108 and 106.
    External spacers 112 are then produced, for example by deposition and etching, on the stack 102, and against the lateral flanks of the dummy grid 110. These external spacers 112 are notably arranged above parts of the layers 108 intended to be find in the source and drain extension regions, that is to say between the channel and the source and drain regions of the device 100. The length, or depth, of these spacers (dimensions parallel to the axis X represented in FIG. 1A) is for example between approximately 3 and 8 nm.
    The parts of the stack 102 not covered by the dummy grid 110 and by the external spacers 112 are then etched (FIG. 1B). The remaining portions of the layers 108 form nanowires 114 of the channel of the device 100. Each of the nanowires 114 is interposed between two remaining portions 116 of the layers 106.
    As shown in FIG. 1C, source and drain regions 118, 120 are then formed by epitaxy on the substrate 104, from the ends of the nanowires 114 and of the portions 116 and of the bulk substrate 104. These regions 118, 120 are produced with in-situ doping so as to obtain a good junction quality. For example, the doping of the material of regions 118, 120 can be carried out with boron doping atoms whose concentration is for example between approximately 10 18 and 10 21 at / cm 3 . The material of the source and drain regions 118, 120 is here SiGe: B.
    In the first embodiment described here, the source and drain regions 118, 120 comprise SiGe. The germanium concentration of SiGe in the source and drain regions 118, 120 is for example between approximately 20% (Sio, 8Geo, 2) θΐ 80%. (Sio, 2Geo, s)
    In this first embodiment, internal spacers of the device 100 are intended to be produced by oxidation of portions of the source and drain regions 118, 120. However, this oxidation will also impact the semiconductor of the nanowires 114. So that the setting implementation of this oxidation does not transform into oxide all of the semiconductor of the nanowires 114 of the channel, the material of the source and drain regions 118, 120 is chosen such that its oxidation speed is greater than that of the material of the nanowires 114. Thus, in the embodiment described here, this property is obtained by producing silicon nanowires 114 and source and drain regions of SiGe with a germanium concentration of between approximately 20% and 80% . In general, in a P-type transistor, the germanium concentration in the semiconductor of the source and drain regions 118, 120 may be higher than that in the semiconductor of nanowires 114.
    The higher the concentration of germanium in the SiGe of the source and drain regions 118, 120, the faster this semiconductor of the source and drain regions 118, 120 will oxidize compared to the semiconductor of nanowires 114, and / or higher the temperature at which the oxidation is carried out may be low.
    In addition, the material of the source and drain regions 118, 120 is also chosen such that it is more resistant than that of the layers 106 with respect to the etching implemented subsequently to remove the remaining portions 116 of the layers. 106 and release the nanowires 114. Thus, when the layers 106 and the source and drain regions 118, 120 comprise SiGe, the germanium concentration in the SiGe of the source and drain regions 118, 120 is advantageously lower than that in the SiGe of layers 106, and preferably at least 5% or at least 10% lower than that of SiGe in layers 106. This difference in germanium concentration is preferably observed at least in part of the source and drain regions 118, 120 lying against the ends of the nanowires 114 and portions 116 serving for the epitaxy of the source and drain regions 118, 120. The material forming the remainder of the source and drain regions 118, 120 can be d different, both in terms of germanium concentration and doping.
    In this first embodiment, because the epitaxy forming the source and drain regions 118, 120 is implemented from the ends of the remaining portions 116 and of the nanowires 114 which together form a continuous crystal surface, and optionally from the substrate 104 when the latter comprises a crystalline semiconductor, each of the source and drain regions 118, 120 obtained forms a semiconductor crystal coherent with the remaining portions of the layers 106, 108 and possibly with the substrate 104 when this includes a crystalline semiconductor. It is thus possible to introduce into the source and drain regions 118, 120 a difference in mesh parameters, thus inducing a stress in the channel of the device 100.
    Encapsulation material 122 is then deposited on the source and drain regions 118, 120 (FIG. 1D) so as not to alter these regions during the implementation of the subsequent steps.
    The dummy grid 110 is then etched, revealing the nanowires 114 and also forming accesses to the portions 116. A selective etching of the remaining portions 116 with respect to the nanowires 114, the source and drain regions 118, 120 and the spacers 112 are then implemented in order to release the nanowires 114 forming the channel of transistor 100. In addition, the etching of the remaining portions 116 forms cavities 124 at the locations previously occupied by the ends of the remaining portions 116 of the layers 106 covered by the external spacers 112, in the source and drain extension regions (Figure 1E). This etching corresponds for example to a chemical etching HCI / H2.
    The bottom walls of these cavities 124 are formed by the source and drain regions 118, 120. These walls are self-aligned with respect to each other, and aligned one above the other because they have been defined by the implementation of the etching of the stack 102 eliminating the portions of the stack 102 not covered by the dummy grid 110 and by the external spacers 112.
    An oxidation of portions of the source and drain regions 118, 120, from the surfaces forming the bottom walls of the cavities 124, is then implemented. This oxidation forms, at the level of source and drain extension regions, internal spacers 126 comprising a dielectric material with low permittivity (low-k) and intended to isolate these regions from the grid which will be produced. later (Figure 1F).
    Because the internal spacers 126 are formed by oxidation, a first part of the oxide forming these spacers 126 (about 50%) is formed within the source and drain regions 118, 120, and a second part of the oxide forming the spacers 126 (about 50%) grows in an opposite direction (direction going from the bottom walls of the cavities 124 towards the location for the grid), in the source and drain extension regions which are surrounded by the external spacers 112. The length, or depth (dimension parallel to the X axis), of each internal spacer 126 is for example equal to approximately 6 nm.
    During this oxidation, part of the nanowires 114 oxidizes. However, because of the materials used (silicon nanowires 114 and source and drain regions 118, 120 in SiGe), the oxidation of nanowires 114 is slower than that of the portions of source and drain regions 118, 120 being at the bottom of the cavities 124 and intended to form the internal spacers 126. In the first embodiment described here, this difference in oxidation rate is due to the high germanium concentration in the source and drain regions 118, 120 which allows an oxidation of SiGe faster than that of silicon in nanowires 114. For example, considering SiGe whose germanium concentration is equal to approximately 50% (Sio, 5Geo, s) and an oxidation forming an oxide of equal thickness at approximately 10 nm, the oxide thickness obtained by the implementation of this oxidation on silicon is between approximately 1 nm and 6 nm (thickness varying in particular depending on whether a native oxide is present on the surface of the silicon of the nanowires 114, or that nanowires 114 have previously undergone deoxidation, for example with an HF solution, removing this native oxide).
    Preferably, this oxidation is carried out at a low temperature of between approximately 700 ° C and 900 ° C in order to avoid diffusion of the dopants in the channel of the device 100. In addition, the lower the temperature at which the oxidation is implementation is low, the greater the oxidation selectivity obtained thanks to the different dopings and / or to the different compositions of the oxidized materials.
    In certain cases, higher temperatures can however be envisaged since an increase in the temperature for carrying out the oxidation allows faster oxidation of the materials. For example, by carrying out the oxidation at a temperature of approximately 1100 ° C. on Sio, sGeo, 5, an oxide thickness of approximately 8 nm is obtained after 1 second of oxidation, the thickness d oxide formed on silicon being 4 nm for the same oxidation time.
    The higher the germanium concentration in the source and drain regions 118, 120, the greater the selectivity of the oxidation with respect to the semiconductor of the nanowires 114. Significant selectivity in particular gives greater latitude in the choice of the duration and the temperature for carrying out the oxidation.
    This oxidation is, for example, a plasma-assisted oxidation or a dry oxidation in the presence of oxygen, or else annealing in an oxidizing atmosphere.
    Then, the oxide thickness formed around, or at the ends, of the nanowires 114 is removed by etching. When germanium oxide is removed, it is possible to implement a method as described in the document “Selective GeOx-Scavenging from Interfacial Layer on Sii-xGex Channel for High Mobility Si / Sii-xGex CMOS Application” CH Lee et al., 2016 Symposium on VLSI Technology Digest of Technical Papers, pages 36-37.
    This etching also impacts the semiconductor oxide of the internal spacers 126 and therefore also removes a similar thickness of oxide from the internal spacers 126. At the end of this etching, the internal spacers 126 have a length, or depth, corresponding with the difference between the initial length of the internal spacers 126 and the thickness of oxide eliminated by the implementation of this etching, and for example between approximately 1 nm and 2.5 nm.
    A grid 128, comprising at least one grid dielectric and a grid conductive material, is then produced between the external spacers 112, at the location previously occupied by the dummy grid 110 (Figure IG). The grid 128 thus produced surrounds the nanowires 114 and is electrically isolated from the source and drain regions 118, 120 by the internal spacers 126 and the external spacers 112.
    Thus, the internal spacers 126 make it possible to reduce the capacitive effects between the gate 128 and the source and drain regions 118, 120.
    The device 100 is completed by removing the encapsulation material 122 and by forming electrical contacts 130, 132 and 134 on the source and drain regions 118, 120 and on the grid 128 (FIG. 1H).
    We will now describe a method for producing a semiconductor device 100, corresponding here to a P-type GAA-FET transistor, according to a second embodiment.
    The steps previously described in connection with Figures IA and IB are first implemented.
    The portions 116 are then selectively etched with respect to the other materials present (this selective etching being possible thanks to the fact that the germanium concentration in the semiconductor of the layers 106 is higher than that in the semiconductor of the layers 108), forming cavities 136 between which the nanowires 114 are located (FIG. 2A).
    A material capable of being selectively etched with respect to the nanowires 114, the source and drain regions 118, 120 and the external spacers 112, is then deposited in the cavities 136, forming portions 138 between which the nanowires 114 are arranged (FIG. 2B).
    The process is then completed in a manner analogous to the first embodiment, that is to say by implementing the steps previously described in connection with FIGS. 1H to 1H.
    In this second embodiment, the material of the initial stack located between the nanowires of the device 110 is replaced by another material. Thus, this second embodiment can be implemented when the desired material between the nanowires cannot be obtained during the production of the stack of layers 106, 108.
    The material of the portions 138 corresponds for example to a semiconductor such as SiGe with a high concentration of germanium, or else germanium. For example, when the source and drain regions 118, 120 are intended to be produced subsequently in SiGe, the germanium concentration in the SiGe of the portions 138 may be at least 20% higher than that of the SiGe of the regions source and drain 118, 120. In this case, the portions 138 can be formed via a selective deposition process such that the material of the portions 138 is deposited only around the nanowires 114.
    As a variant, the material of the portions 138 can be a dielectric material such as S1O2, such a dielectric material cannot be found initially in a stack of crystalline layers formed by epitaxy. In this case, the dielectric material deposited outside the cavities 136 (due to the non-selective deposit which is used to form such portions) is removed before the process is continued.
    For the first and second embodiments, it is possible that the source and drain regions 118, 120 are obtained by implementing several epitaxies allowing the growth of materials of different compositions (for example by varying the concentration of germanium between the epitaxies) and / or different dopant concentrations. For example, the production of the source and drain regions 118, 120 may comprise the implementation of a first epitaxy of SiGe comprising carbon atoms, then of a second epitaxy of SiGe not comprising carbon atoms. Thus, since the epitaxy is implemented with in situ doping of the source and drain regions 118, 120 formed, the portion of SiGe comprising carbon atoms formed initially makes it possible to reduce the diffusion of dopants in the region channel of device 100.
    Another advantageous variant, for producing a P-type transistor, may consist in producing the source and drain regions by implementing a first epitaxy of SiGe with a high germanium concentration (for example between approximately 40% and 60%), then a second epitaxy of SiGe with a lower germanium concentration (for example between approximately 20% and 30%).
    Thus, when the internal spacers 126 are produced by oxidation, the thickness of the SiGe with a high germanium concentration will form an oxidation depth limit for the internal spacers 126 which will be obtained, thus allowing self-limitation of the length, or depth, internal spacers 126 in the source and drain regions 118,120.
    Such self-limitation of the depth of the internal spacers can also be obtained, for the production of an N-type transistor, by implementing a first epitaxy of Si with a high concentration of P or As dopants, then a second epitaxy of Si with a lower concentration of dopants. Thus, during the production of the internal spacers 126 by oxidation, the thickness of the highly doped silicon will form an oxidation depth limit for the internal spacers 126 which will be obtained.
    The method according to the various embodiments previously described can be implemented to form a device 100 corresponding to an N-type transistor. In this case, the material of the layers 108 (and therefore also the material of the nanowires 114) and that of the source and drain regions 118, 120 obtained by epitaxy can correspond to silicon or SiGe. When the source and drain regions 118, 120 comprise silicon, the difference required between the oxidation speed of the material of the source and drain regions 118, 120 and that of the material of the nanowires 114 is obtained for example by strongly doping the silicon of the source and drain regions 118, 120 by dopants of the phosphorus or arsenic type which give the silicon of the source and drain regions 118, 120 the desired electrical properties and an ability to oxidize more quickly than non-doped silicon intentionally.
    For example, for an oxidation of phosphorus-doped silicon (Si: P) with a dopant concentration of approximately 3.10 20 at / cm 3 implemented at approximately 800 ° C, an oxide layer of thickness equal to approximately 10 nm is formed after approximately 10 minutes of carrying out the oxidation. For intentionally undoped silicon (concentration of dopants equal to approximately 10 15 at / cm 3 ), an oxidation implementation period of approximately 60 minutes is necessary to obtain an oxide thickness of approximately 10 nm .
    As a variant, an N-type transistor can be produced using, instead of silicon, SiGe.
    The characteristics of the oxidation implemented as a function of the crystalline orientation of the semiconductors used are described for example in the document "The Effect of Surface Orientation on Silicon Oxidation Kinetics" by E. A. Lewis et al., J. Electrochem. Soc. 1987, vol. 134, issue 9, pp. 2332-2339.
    A method of producing a P-type transistor is now described, according to a third embodiment.
    The steps previously described in connection with Figures IA to 1F are first implemented.
    Then, the nanowires 114 are thinned by at least a thickness of between approximately 1 nm and 3 nm in order to expose parts 140 from the layers 108 located in the source and drain extension regions (parts of semiconductor surrounded by the external spacers 112) and which are arranged between the internal spacers 126 (FIG. 3A). This thinning can be obtained by implementing an oxidation of the semiconductor of the nanowires 114 then an etching of the oxidized semiconductor. These steps can be implemented simultaneously, or during the same set of steps, with the oxidation and etching steps forming the internal spacers 126.
    An epitaxy of SiGe is then implemented on the thinned nanowires 114 (FIG. 3B). The epitaxial layers of SiGe 142 surround the remaining silicon portion of each nanowire 114. Advantageously, the thickness of the epitaxial layer of SiGe 142 is substantially equal to the thickness of the semiconductor etched to form the thinned nanowires. Thus, the outer edges of the SiGe layer are aligned with the initial interfaces (before thinning) between the internal spacers 126 and the nanowires 114.
    A thermal annealing can then be implemented so as to diffuse the germanium of the layers 142 in the silicon of the nanowires 114 in order to obtain a more homogeneous material forming the channel of the device 100. This annealing can also modify the semiconductor found in the source and drain extension regions (portions of semiconductor coming from the layers 108 and being between the internal spacers 126) due to the migration of germanium which can come from the layers 142 or else from the source and drain 118, 120, allowing a more homogeneous material to be obtained also in the source and drain extension regions.
    The method is then completed as previously described for the first embodiment, that is to say by implementing the steps previously described in connection with Figures IG and 1H.
    In this third embodiment, the layer 142 of SiGe forms, around the silicon of the thinned nanowire 114, a semi-conductor constrained in compression.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Method for producing a semiconductor device (100), comprising at least the implementation of the following steps:
    - Realization, on a substrate (104), of a stack (102) comprising at least a first portion (108,114) of crystalline semiconductor intended to form a channel of the semiconductor device (100) and arranged on at least one second portion (106, 116) of at least one material capable of being selectively etched with respect to the semiconductor of the first portion (108,114),
    - production, on part of the stack (102), of a dummy grid (110) and external spacers (112) between which the dummy grid (110) is disposed,
    - etching of the stack (102) such that only a remaining part of the stack (102) covered by the dummy grid (110) and by the external spacers (112) is preserved,
    - Realization of source and drain regions (118,120) by semiconductor epitaxy from at least the remaining part of the stack (102),
    - elimination of the dummy grid (110) and of the second portion (116),
    - oxidation of portions of the source and drain regions (118, 120) from portions of a face of each of the source and drain regions (118, 120) revealed by the removal of the second portion (116), the portions oxidized forming internal spacers (126),
    - Production of a grid (128) between the external spacers (112), covering the channel and electrically isolated from the source and drain regions (118, 120) by the external spacers (112) and the internal spacers (126).
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which the semiconductor of the source and drain regions (118, 120) is able to oxidize more quickly than the semiconductor of the first portion (108,114).
    [3" id="c-fr-0003]
    3. Method according to claim 2, in which:
    - when the semiconductor device (100) is an N-type transistor, the semiconductor of the first portion (108, 114) is intentionally undoped and the production of the source and drain regions (118,120) includes doping N-type semiconductor in the source and drain regions (118,120), or
    - when the semiconductor device (100) is a P-type transistor, the semiconductor of the first portion (108, 114) is silicon or SiGe, and the semiconductor of the source and drain regions ( 118,120) is SiGe having a higher proportion of germanium than that of the semiconductor of the first portion (108, 114).
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, in which, when the semiconductor device (100) is a P-type transistor, the material of the second portion (106, 116) is SiGe, and a proportion of germanium in the semiconductor of the source and drain regions (118, 120) is at least 5% lower than that in the SiGe of the second portion (106,116).
    [5" id="c-fr-0005]
    5. Method according to one of the preceding claims, in which the oxidation of the portions of the source and drain regions (118,120) is carried out at a temperature between about 700 ° C and 900 ° C.
    [6" id="c-fr-0006]
    6. Method according to one of the preceding claims, further comprising the implementation, between the steps of oxidizing the portions of the source and drain regions (118, 120) and producing the grid (128), the implementation of a step of removing an oxidized part of the material from the first portion (114).
    [7" id="c-fr-0007]
    7. The method of claim 6, further comprising, after the removal of the oxidized part of the material from the first portion (114), a step of depositing a constrained semiconductor material (142) around the first portion (114 ).
    [8" id="c-fr-0008]
    8. Method according to one of the preceding claims, further comprising, between the step of etching the stack (102) and the step of producing the source and drain regions (118, 120), the implementation of stages of:
    - deletion of the second portion (116),
    - Deposit of at least one material (138), different from that of the second portion (116) and capable of being selectively etched with respect to the semiconductor of the first portion (114), in at least one space (136 ) formed by the removal of the second portion (116), and in which the material (138) deposited in the space (136) formed by the removal of the second portion (116) is removed after the removal of the dummy grid ( 110).
    [9" id="c-fr-0009]
    9. Method according to one of the preceding claims, in which the production of the source and drain regions (118, 120) comprises at least the implementation of a first epitaxy from the remaining part of the stack (102) , forming a first part of the source and drain regions (118, 120), then a second epitaxy from the first part of the source and drain regions (118, 120), forming a second part of the source and drain regions (118,120).
    [10" id="c-fr-0010]
    10. The method of claim 9, wherein the first epitaxy is implemented such that the first part of the source and drain regions (118, 120) comprises a semiconductor capable of oxidizing faster than that of the second part of the source and drain regions (118,120).
    [11" id="c-fr-0011]
    11. The method of claim 10, wherein the first epitaxy is implemented such that the first part of the source and drain regions (118, 120) comprises semiconductor including carbon atoms, and / or in which , when the source and drain regions (118, 120) comprise SiGe, the first and second epitaxy are implemented such that the proportion of germanium in the semiconductor of the first part of the source and drain regions ( 118,120) is greater than that in the semiconductor of the second part of the source and drain regions (118,120).
    [12" id="c-fr-0012]
    12. Method according to one of the preceding claims, in which the second portion (106, 116) comprises a crystalline material, and the epitaxy forming the source and drain regions (118,120) is carried out from at least the crystalline materials of the second portion (116) and the first portion (114).
    [13" id="c-fr-0013]
    13. Method according to one of the preceding claims, in which
    10 the epitaxy of the source and drain regions (118, 120) is implemented such that the semiconductors of the source and drain regions (118, 120) and of the first portion (114) have a difference in parameters of mesh inducing a stress in the channel.
    [14" id="c-fr-0014]
    14. Method according to one of the preceding claims, in which the stack (102) produced initially comprises several first portions (108) of semiconductor each forming a nanowire (114) disposed between two second portions (116).
    [15" id="c-fr-0015]
    15. Method according to one of the preceding claims, in which the semiconductor device (100) is a GAA-FET transistor.
    S.60521
    1/5
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    2018-06-22| PLSC| Publication of the preliminary search report|Effective date: 20180622 |
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    优先权:
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    FR1662532A|FR3060841B1|2016-12-15|2016-12-15|PROCESS FOR MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS|
    FR1662532|2016-12-15|FR1662532A| FR3060841B1|2016-12-15|2016-12-15|PROCESS FOR MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS|
    US15/837,217| US10269930B2|2016-12-15|2017-12-11|Method for producing a semiconductor device with self-aligned internal spacers|
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